In a memory cell of a nonvolatile semiconductor memory device such as a flash memory (flash E2PROM), threshold voltage of a transistor as a component of the memory cell changes between a data erasure state and a data non-erasure state.
Usually, for example, when data is erased in a memory cell in a flash memory which is used, the threshold voltage becomes low and cell current increases. Consequently, when erasure advances in even one memory cell, current in an entire memory cell array largely flows.
That is, in a general flash memory, in batch verification of performing wired-OR operation on bit lines of all of memory cells, for example, if even one memory cell in the erasure state exists, the potential of the bit line is decreased to the level of a low-potential power supply line. Consequently, it is difficult to detect that all of memory cells are erased in a lump.
As a result, in a flash memory using a memory cell whose threshold voltage becomes low when data is erased, erase verification is performed address by address like in the reading operation.
In a nonvolatile semiconductor device such as a flash memory (flash E2PROM) using, for example, a memory cell whose threshold voltage becomes low when data is erased, even when batch erasure is executed on a plurality of sectors, verification time is long. Consequently, there is a problem such that the effect of the batch erasure is reduced.
For example, a nonvolatile semiconductor memory device including large storage capacity may have a problem to be solved such that verification time is unignorably long.
In the related art, there have been proposed various kinds of verification techniques for a nonvolatile semiconductor memory device.
Patent Document 1: Japanese Laid-open Patent Publication No. H03-259499
Patent Document 2: Japanese Laid-open Patent Publication No. H10-241378
Patent Document 3: Japanese Laid-open Patent Publication No. H10-228785
Patent Document 4: Japanese Laid-open Patent Publication No. H07-057482